By Dr.-Ing. Keh-La Lin, Armin Kemna, Prof. Bedrich J. Hosticka (auth.)

One of the most developments of microelectronics is towards layout for built-in structures, i.e., system-on-a-chip (SoC) or system-on-silicon (SoS). because of this improvement, layout concepts for mixed-signal circuits turn into extra vital than ahead of. between different units, analog-to-digital and digital-to-analog converters are the 2 bridges among the analog and the electronic worlds. in addition to, low-power layout process is likely one of the major concerns for embedded platforms, in particular for hand held applications.

Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems goals at layout recommendations for low-power, high-speed analog-to-digital converter processed by way of the traditional CMOS know-how. also this publication covers actual integration problems with A/D converter built-in in SoC, i.e., substrate crosstalk and reference voltage community layout.

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Additional info for Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems

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E. 2). The architectures without feedback have more advantages concerning to the high-speed conversion. Details of each architecture will be shown in the following. 1 Flash A/D Converter Analog-to-Digital Conversion 25 The well-known flash A/D converter represents the classical high-speed A/D converter architecture [4, 10, 14-17]. 3 V [19]. An embedded implementation [20] for a mixed-signal single chip fabricated in technology for DVD systems contains a 7-bit flash ADC, a 32-bit RISC CPU, servo DSP and 16 Mb DRAM.

This kind of design reduces substantially both the power dissipation and the die area of high-speed comparators for the high-resolution A/D converter. A drawback of the folding and interpolating A/D converter, which is mentioned very often in the literature [47, 70, 74, 75], is the internal frequency generated by the folding stage. This problem can be better understood when considering the same 8-bit A/D converter in 3/5-architecture described above. Providing that the input signal of the folding stage is a saw-tooth signal as depicted in Fig.

2 Estimate of Theoretical Quantization Error To estimate the value of the quantization error methods like the mean square error and the root-mean-square error (RMS error) are usually employed in the open literature. This allows the computation of the absolute value of the error without canceling its positive values by negative ones. The definition of the mean square error can be described as follows [8, 9]: Chapter 2 18 where the function g(x) is the approximation function of the function f (x) and the interval [a, b] indicates where the approximation has been applied.

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